Previously we mentioned about PCI Express version 3.0 specifications that has been pushed out multiple times, now the industry specifications has finally been approved and posted to PCI-SIG website.

The PCI Express is one of the commonly available high performance interface standards that been widely deployed in today’s PC and embedded world. It continues to be useful in all the market segments including mobile computing, desktop, server and workstation based applications where a high bandwidth transmission and connectivity are required. With current PCI Express version 2.0 that capped at 5GT/s, the new version 3.0 has able to boost it further to 8GT/s while still maintaining backward compatibility to existing PCI Express 2.0 or even 1.0 peripherals. The high transmission is made possible thanks to its new 128b/130b data encoding scheme that eliminates overhead with 100% efficiency. Based on theoretical calculation, a x1 configuration can support up to 1GB/s in uni-direction transfer with ability to scale up to 32GB/s when a x16 lane configuration is used. Besides higher data transmission, there are a few other enhancements ranging from atomic operations, data reuse hints, latency tolerance reporting, BAR resizing, dynamic power adjustment mechanisms that can easily optimized and fitted into various usage models with flexible architecture scalability.

Currently PCI Express Base 3.0 specification is already available for download at PCI-SIG for registered members and we should expect new PCI Express 3.0 compliant devices available by 2011.